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| Microcomputer Components 8-Bit Single-Chip Microcontroller Family SAB 80515 / SAB 80535 Data Sheet 08.95 SAB 80515 / 80535 Data Sheet Revision History: Current Version: 08.95 Previous Version: 09.89, 11.92 Page Subjects (changes since last revision) 1, 2, 27, - 40 to + 110 C version deleted; Note: only on request ... added 29, 30 tC and Vint ERROR modified 29 Header of table (16 MHz) corrected 36 Edition 08.95 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. High-Performance 8-Bit Single Chip Microcontroller Preliminary SAB 80515 SAB 80535 q q q q q q q q q q q q q q q q q SAB 80515/80535 Microcontroller with factory mask-programmable ROM Microcontroller for external ROM 8 K x 8 ROM (SAB 80C515 only) 256 x 8 RAM Six 8-bit I/O ports, one 8-bit input port for analog signals Three 16-bit timer/counters Highly flexible reload, capture, compare capabilities Full-duplex serial channel Twelve interrupt vectors, four priority levels 8-bit A/D converter with 8 multiplexed inputs and programmable internal reference voltages 16-bit watchdog timer VPD provides standby current for 40 bytes of RAM Boolean processo 256-bit-addressable locations Most instructions execute in 1 s (750 ns) 4 s (3 s) multiply and divide External memory expandable up to 128 Kbytes Backwardly compatible with SAB 8051 Two temperature ranges available: 0 to 70 C - 40 to 85 C (T40/85) The SAB 80515/80535 is a powerful member of the Siemens SAB 8051 family of 8-bit microcontrollers. It is fabricated in + 5 V N-channel, silicon-gate Siemens MYMOS technology. The SAB 80515/80535 is a stand-alone, high-performance single-chip microcontroller based on the SAB 8051 architecture. While maintaining all the SAB 8051 operating characteristics, the SAB 80515/80535 incorporates several enhancements which significantly increase design flexibility and overall system performance. The SAB 80535 is identical with the SAB 80515 except that it lacks the on-chip program memory. The SAB 80515/80535 is supplied in a 68-pin plastic leaded chip carrier package (P-LCC-68). Semiconductor Group 3 8.95 SAB 80515/80535 Ordering Information Type SAB 80515-N SAB 80535-N SAB 80515-N-T40/85 SAB 80535-N-40/85 Ordering code Q 67120-C211 Q 67120-C241 Q 67120-C210 Q 67120-C240 Package P-LCC-68 P-LCC-68 P-LCC-68 P-LCC-68 Description 8-bit CMOS microcontroller with mask-programmable ROM for external memory with mask-programmable ROM for external memory Note: Extended temperature range - 40 to 110 C on request Semiconductor Group 4 SAB 80515/80535 Logic Symbol Pin Configuration (P-LCC-68) Semiconductor Group 5 SAB 80515/80535 Pin Definitions and Functions Symbol P4.0-P4.7 Pin 1-3, 5-9 Input (I) Function Output (O) I/O Port 4 is an 8-bit quasi-bidirectional I/O port . Port 4 can sink/source 4 LS-TTL loads. Power down supply. If VPD is held within its specs while VCC drops below specs,VPD will provide standby power to 40 byte of the internal RAM. WhenVPD is low, the RAM's current is drawn from VCC. A low level on this pin for the duration of two machine cycles while the oscillator is running resets the SAB 80C515. A small internal pullup resistor permits power-on reset using only a capacitor connected to V SS Reference voltage for the A/D converter Reference ground for the A/D converter I Multiplexed analog inputs VPD 4 I RESET 10 I V AREF VAGND AN7-AN0 11 12 13-20 Semiconductor Group 6 SAB 80515/80535 Pin Definitions and Functions (cont'd) Symbol P3.0-P3.7 Pin 21-28 Input (I) Function Output (O) I/O Port 3 is an 8-bit bidirectional I/O. It also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. Port 3 can sink/source 4 LS-TTL loads.The secondary functions are assigned to the pins of port 3, as follows: - R x D (P3.0): serial port's receiver data input (asynchronous) or data input/output (synchronous) - T x D (P3.1): serial port's transmitter data output (asynchronous) or clock output (synchronous) - INT0(P3.2): interrupt 0 input/timer 0 gate control input - INT1(P3.3): interrupt 1 input/timer 1 gate control input - T0 (P3.4): counter 0 input - T1 (P3.5): counter 1 input - WR(P3.6): the write control signal latches the data byte from port 0 into the external data memory - RD (P3.7): the read control signal enables the external data memory to port 0 Semiconductor Group 7 SAB 80515/80535 Pin Definitions and Functions (cont'd) Symbol Pin Input (I) Function Output (O) I/O Port 1 is an 8-bit bidirectional I/O port .It is used for the low-order address byte during program verification. It also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: - INT3/CC0 (P1.0): interrupt 3 input / compare 0 output / capture 0 input - INT4/CC1 (P1.1): interrupt 4 input / compare 1 output / capture 1 input - INT5/CC2 (P1.2): interrupt 5 input / compare 2 output / capture 2 input - INT6/CC3 (P1.3): interrupt 6 input / compare 3 output / capture 3 input - INT2(P1.4): interrupt 2 input - T2EX (P1.5): timer 2 external reload trigger input - CLKOUT (P1.6): system clock output - T2 (P1.7): counter 2 input VBB 37 Substrate pin. Must be connected to VSS through a capacitor (47 to 100 nF) for proper operation of the A/D converter. - XTAL2 is the output from the oscillator's amplifier.Input to the internal timing circuitry. A crystal, ceramic resonator, or external source can be used. XTAL1 is the input to the oscillator's high gain amplifier. Required when a crystal or ceramic resonator is used. Connect to VSS when external source is used on XTAL2. P1.7 - P1.0 29 - 36 XTAL2 39 XTAL1 40 - Semiconductor Group 8 SAB 80515/80535 Pin Definitions and Functions (cont'd) Symbol P2.0-P2.7 Pin 41- 48 Input (I) Function Output (O) I/O Port 2 is an 8-bit quasi-bidirectional I/O port. It also emits the high-order address byte when accessing external memory. It is used for the high-order address and the control signals during program verification. Port 2 can sink/source 4 LS-TTL loads. The program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. Remains high during internal program execution. Provides address latch enable output used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. When held at a TTL high level, the SAB 80515 executes instructions from the internal ROM when the PC is less than 8192. When held at a TTL low level, the SAB 80515 fetches all instructions from external program memory. For the SAB 80535 this pin must be tied low. Port 0 is an 8-bit open-drain bidirectional I/O port. It is also the multiplexed low-order address and data bus when using external memory. It is used for data output during program verification. Port 0 can sink/source 8 LS-TTL loads. Port 5 is an 8-bit quasi-bidirectional I/O port. Port 5 can sink/source 4 LS-TTL loads. POWER SUPPLY (+ 5 V power supply during normal operation and program verification) GROUND (0 V) PSEN 49 O ALE 50 O EA 51 I P0.0-P0.7 52-59 I/O P5.7-P5.0 VCC VSS 60-67 68 38 I/O Semiconductor Group 9 SAB 80515/80535 Figure 1 Block Diagram Semiconductor Group 10 SAB 80515/80535 Functional Description The architecture of the SAB 80515 is based on the SAB 8051 microcontroller family. The following features of the SAB 80515 are fully compatible with the SAB 8051 features: - - - - - - Instruction set External memory expansion interface (port 0 and port 2) Full-duplex serial port Timer/counter 0 and 1 Alternate functions on port 3 The lower 128 bytes of internal RAM and the lower 4 Kbytes of internal ROM The SAB 80515 additionally contains 128 bytes of internal RAM and 4 Kbytes of internal ROM, which results in a total of 256 bytes of RAM and 8 Kbytes of ROM on chip. The SAB 80515 has a new 16-bit timer/counter with a 2:1 prescaler, reload mode, compare and capture capability. It also contains a 16-bit watchdog timer, an 8-bit A/D converter with programmable reference voltages, two additional quasi-bidirectional 8-bit ports, one 8-bit input port for analog signals, and a programmable clock output (fOSC/12). Furthermore, the SAB 80515 has a powerful interrupt structure with 12 vectors and 4 programmable priority levels. Figure 1 shows a block diagram of the SAB 80515. CPU The SAB 80515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions execute in 1.0 s. Memory Organization The SAB 80515 manipulates operands in the four memory address spaces described in the following. (Figure 2 illustrates the memory address spaces of the SAB 80515). Semiconductor Group 11 SAB 80515/80535 Figure 2 Memory Address Spaces Semiconductor Group 12 SAB 80515/80535 Program memory The SAB 80515 has 8 Kbyte of on-chip ROM, while the SAB 80535 has no internal ROM. The program memory can be externally expanded up to 64 Kbytes. If the EA pin is held high, the SAB 80515 executes out of internal ROM unless the address exceeds 1FFFH. Locations 2000H through 0FFFFH are then fetched from the external program memory. If the EA pin is held low, the SAB 80515 fetches all instructions from the external program memory. Since the SAB 80535 has no internal ROM, pin EA must be tied low when using this component. Data Memory The data memory address space consists of an internal and an external memory space. The internal data memory is divided into three physically separate and distinct blocks: the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128-byte special function register (SFR) area. While the upper 128 bytes of data memory and the SFR area share the same address locations, they are accessed through different addressing modes. The lower 128 bytes of data memory can be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be accessed through register indirect addressing; the special function registers are accessible through direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers, occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the internal data memory address space, and the stack depth can be expanded up to 256 bytes. The external data memory can be expanded up to 64 Kbytes and can be accessed by instructions that use a 16-bit or an 8-bit address. Semiconductor Group 13 SAB 80515/80535 Special Function Registers All registers, except the program counter and the four 8-register banks, reside in the special function register area. The 41 special function registers (SFR's) include arithmetic registers, pointers, and registers that provide an interface between the CPU and the on-chip peripheral functions. There are also 128 directly addressable bits within the SFR area. The special function registers are listed in the following table: In table 1 they are organized in numeric order of their addresses. In table 2 they are organized in groups which refer to the functional blocks of the SAB 80515/80535. Table 1 Special Function Register Address 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H Register P0 1) SP DPL DPH reserved reserved reserved PCON TCON 1) TMOD TL0 TL1 TH0 TH1 reserved reserved P1 1) reserved reserved reserved reserved reserved reserved reserved Contents after Reset 0FFH 07H 00H 00H XXH 2) XXH 2) XXH 2) 000X 0000B 2) 00H 00H 00H 00H 00H 00H XXH 2) XXH 2) 0FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) Address 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH the location is reserved Register SCON 1) SBUF reserved reserved reserved reserved reserved reserved P2 1) reserved reserved reserved reserved reserved reserved reserved IEN0 1) IP0 reserved reserved reserved reserved reserved reserved Contents after Reset 00H XXXX XXXXB XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 0FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 00H X000 0000B 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 1) Bit-addressable Special Function Register 2) X means that the value is indeterminate and Semiconductor Group 14 SAB 80515/80535 Table 1 Special Function Register (cont'd) Address B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH Register P31) reserved reserved reserved reserved reserved reserved reserved IEN1 1) IP1 reserved reserved reserved reserved reserved reserved IRCON 1) CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 T2CON 1) reserved CRCL CRCH TL2 TH2 reserved reserved Contents after Reset 0FFH XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) 00H XX00 0000B 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2 00H 00H 00H 00H 00H 00H 00H 00H 00H XXH 2) 00H 00H 00H 00H XXH 2) XXH 2) Address D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH the location is reserved Register PSW 1) reserved reserved reserved reserved reserved reserved reserved ADCON ADDAT DAPR P6 reserved reserved reserved reserved ACC 1) reserved reserved reserved reserved reserved reserved reserved P4 1) reserved reserved reserved reserved reserved reserved reserved Contents after Reset 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 00X0 0000B 2) 00H 00H XXH 2) XXH 2) XXH 2) XXH 2) 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 0FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 1) Bit-addressable Special Function Register 2) X means that the value is indeterminate and Semiconductor Group 15 SAB 80515/80535 Table 1 Special Function Register (cont'd) Address F0H F1H F2H F3H F4H F5H F6H F7H 1) 2) Register B1) reserved reserved reserved reserved reserved reserved reserved Contents after Reset 00H XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) XXH2) Address F8H F9H FAH FBH FCH FDH FEH FFH Register P5 1) reserved reserved reserved reserved reserved reserved reserved Contents after Reset 0FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) Bit-addressable Special Function Register X means that the value is indeterminate and the location is reserved Semiconductor Group 16 SAB 80515/80535 Table 2 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP Name Accumululator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Address 0E0H 1) 0F0H 1) 083H 082H 0D0H 1) 081H 0D8H 1) 09DH 0DAH 0A8H 1) 0B8H 1) 0A9H 0B9H 0C0H 1) 1) 88H 0C8H 1 0C1H 0C3H 0C5H 0C7H 0C2H 0C4H 0C6H 0CBH 0CAH 0CDH 0CCH 0C8H 1) Contents after Reset 00H 00H 00H 00H 00H 07H 00X0 0000B 3) 00H 00H) 00H 00H X000 0000B 3) XX00 0000B 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H A/DConverter Interrupt System ADCON 2) A/D Converter Control Register A/D Converter Data Register ADDAT A/D Converter Program Register DAPR IEN0 2) IEN1 2) IP0 2) IP1 IRCON TCON 2) T2CON 2) CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON 2) Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register Timer Control Register Timer 2 Control Register Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2. Low Byte Comp./Capture Reg. 3, Low Byte Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register 1) Compare/ CaptureUnit Compare/ CaptureUnit (CCU) (cont'd) (CCU) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3) X means that the value is indeterminate Semiconductor Group 17 SAB 80515/80535 Table 2 Special Function Registers- Functional Blocks (cont'd) Block Ports Symbol P0 P1 P2 P3 P4 P5 P6 PCON 2) ADCON 2) PCON 2) SBUF SCON TCON 2) TH0 TH1 TL0 TL1 TMOD IEN0 2) IEN1 2) IP0 2) Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6, Analog/Digital Input Power Control Register A/D Converter Control Reg. Power Control Register Serial Channel Buffer Reg. Serial Channel Control Reg. Timer Control Register Timer 0. High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte TImer Mode Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Address 80H 1) 90H 1) 0A0H 1) 0B0H 1) 0E8H 1) 0F8H 1) 0DBH 087H 0D8H 1) 087H 099H 098H 1) 088H1) 08CH 08DH 08AH 08BH 089H 0A8H 1) 0B8H 1) 0A9H Contents after Reset 0FFH 0FFH 0FFH 0FFH 0FFH 0FFH 000X 0000 B 2) 00X0 0000B 3) 000X 0000B 3) XXXX XXXXB 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H X000 0000B 3) Pow. Sav. Modes Serial Channels Timer 0/ Timer 1 Watchdog 1) 2) 3) Bit-addressable special function registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks. X means that the value is indeterminate and the location is reserved Semiconductor Group 18 SAB 80515/80535 Serial Port The serial port of the SAB 80515 enables full duplex communication between microcontrollers or between microcontroller and peripheral devices. The serial port can operate in 4 modes: Mode 0: Shift register mode. Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 of the oscillator frequency. Mode 1: 10 bits are transmitted (through RxD) or received (through TxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). The baud rate is variable. Mode 2: 11 bits are transmitted (through RxD) or received (through TxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). Mode 3 is identical to mode 2 except for the baud rate. The baud rate in mode 3 is variable. The variable baud rates in modes 1 and 3 can be generated by timer 1 or an internal baud rate generator. A/D Converter The 8-bit A/D converter of the SAB 80515 has eight multiplexed analog inputs (Port 6) and uses the successive approximation method. It takes 5 machine cycles to sample an analog signal (during this sample time the input signal should be held constant); the total conversion time (including sample time) is 15 machine cycles (15 s at 12 MHz oscillator frequency). Conversion can be programmed to be single or continuous; at the end of a conversion an interrupt can be generated. A unique feature is the capability of internal reference voltage programming. The internal reference voltages VIntAREF and VIntAGND for the A/D converter both are programmable to one of 16 steps with respect to the external reference voltages. This feature permits a conversion with a smaller internal reference voltage range to gain a higher resolution. In addition, the internal reference voltages can easily be adapted by software to the desired analog input voltage range. Figure 3 shows a block diagram of the A/D converter. Semiconductor Group 19 SAB 80515/80535 Figure 3 Block Diagram of the A/D Converter Semiconductor Group 20 SAB 80515/80535 Timer/Counters The SAB 80515 contains three 16-bit timer/counters which are useful in many applications for timing and counting. The input clock for each timer/counter is 1/12 of the oscillator frequency in the timer operation or can be taken from an external clock source for the counter operation (maximum count rate is 1/24 of the oscillator frequency). - Timer/counter 0 and 1 These timer/counters can operate in four modes: Mode 0: 8-bit timer/counter with 32:1 prescaler Mode 1: 16-bit timer/counter Mode 2: 8-bit timer/counter with 8-bit auto-reload Mode 3: Timer/counter 0 is configured as one 8-bit timer/counter and one 8-bit timer; timer/counter 1 in this mode holds its count. External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0 and 1 to facilitate pulse width measurements. - Timer/counter 2 Timer/counter 2 of the SAB 80515 is a 16-bit timer/counter with several additional features. It offers a 2:1 prescaler, a selectable gate function, and compare, capture and reload functions. Corresponding to the 16-bit timer register there are four 16-bit capture/compare registers, one of them can be used to perform a 16-bit reload on a timer overflow or external event. Each of these registers corresponds to a pin of port 1 for capture input/compare output. Figure 4 shows a block diagram of the timer/counter 2. Reload A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the 8-bit registers CRCL and CRCH. There are two modes from which to select: Mode 0: Reload is caused by a timer 2 overflow (auto-reload). Mode 1: Reload is caused in response to a negative transition at pin T2EX (P1.5), which can also request an interrupt. Capture This feature permits saving the actual timer/counter contents into a selected register upon an external event or a software write operation. Two modes are provided to latch the current 16bit value in timer 2 registers into a dedicated capture register: Mode 0: Capture is performed in response to a transition at the corresponding port 1 pins CC0 to CC3. Mode 1: Write operation into the low-order byte of the dedicated capture register causes the timer 2 contents to be latched into this register. Semiconductor Group 21 SAB 80515/80535 Compare In the compare mode, the 16-bit values stored in the dedicated compare registers are compared to the contents of the timer 2 registers. If the count value in the timer 2 registers matches one of the stored values, an appropriate output signal is generated and an interrupt is requested. Two compare modes are provided: Mode 0: Upon a match the output signal changes from low to high. It goes back to a low level when timer 2 overflows. Mode 1: The transition of the output signal can be determined by software. A timer 2 overflow causes no output change. Semiconductor Group 22 SAB 80515/80535 Figure 4 Block Diagram of Timer/Counter 2 Semiconductor Group 23 SAB 80515/80535 Interrupt Structure The SAB 80515 has 12 interrupt vectors with the following vector addresses and request flags: Table 3 Interrupt Sources and Vectors Source (Request Flags) IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 IADC IEX2 IEX3 IEX4 IEX5 IEX6 Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH Vector External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt A/D converter interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Each interrupt vector can be individually enabled/disabled. The minimum response time to an interrupt request is more than 3 machine cycles and less than 9 machine cycles. Figure 5 shows the interrupt request sources. External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable) at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering on a negative or a positive transition. The external interrupts 3 to 6 are combined with the corresponding alternate functions compare (output) and capture (input) on port 1. For programming of the priority levels the interrupt vectors are combined to pairs. Each pair can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register IP0 and one in IP1. Figure 6 shows the priority level structure. Semiconductor Group 24 SAB 80515/80535 Figure 5 Interrupt Request Sources Semiconductor Group 25 SAB 80515/80535 Figure 6 Priority Level Structure Semiconductor Group 26 SAB 80515/80535 I/O Ports The SAB 80515 has six 8-bit I/O ports and one 8-bit input port. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 5 are quasi-bidirectional I/O ports with internal pull-up resistors. That means, when configured as inputs, ports 1 to 5 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. Port 0 and port 2 can be used to expand the program and data memory externally. During an access to external memory, port 0 emits the low-order address byte and reads/writes the data byte, while port 2 emits the high-order address byte. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET. Ports 1 and 3 are provided for several alternate functions, as listed below: Port P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Symbol INT3/CC0 INT4/CC1 INT5/CC2 INT6/CC3 INT2 T2EX CLKOUT T2 RXD TXD INT0 INT1 T0 T1 WR RD Function External interrupt 3 input, compare 0 output, capture 0 input External interrupt 4 input, compare 1 output, capture 1 input External interrupt 5 input, compare 2 output, capture 2 input External interrupt 6 input, compare 3 output, capture 3 input External interrupt 2 input Timer 2 external reload trigger input System clock output Timer 2 external counter input Serial port's receiver data input (asynchronous) or data input/output (synchronous) Serial port's transmitter data output (asynchronous) or clock output (synchronous) External interrupt 0 input, timer 0 gate control External interrupt 1 input, timer 1 gate control Timer 0 external counter input Timer 1 external counter input External data memory write strobe External data memory read strobe The input port AN0-AN7 is used for analog input signals to the A/D converter. Semiconductor Group 27 SAB 80515/80535 Watchdog Timer This feature is provided as a means of graceful recovery from a software upset. After an external reset, the watchdog timer is cleared and stopped. It can be started and cleared by software, but it cannot be stopped. If the software fails to clear the watchdog timer at least every 65532 machine cycles (about 65 ms if a 12 MHz oscillator frequency is used), an internal hardware reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software. To clear the watchdog, two bits in two different special function registers must be set by two consecutive instructions (bits IEN0.6 and IEN1.6). This is done to prevent the watchdog from being cleared by unexpected opcodes. Instruction Set Summary The SAB 80515/80535 has the same instruction set as the industry standard 8051 microcontroller. A pocket guide is available which contains the complete instruction set in functional and hexadecimal order. Furtheron it provides helpful information about Special Function Registers, Interrupt Vectors and Assembler Directives. Literature Information Title Microcontroller Family SAB 8051 Pocket Guide Ordering No. B158-B6599 - X - X - 7600 Semiconductor Group 28 SAB 80515/80535 Absolute Maximum Ratings Ambient temperature under bias SAB 80515/80535 ............................................................................................. 0 to 70 C SAB 80515/80535-T40/85................................................................................. - 40 to 85 C Storage temperature ......................................................................................... - 65 to 150 C Voltage on any pins with respect to ground (VSS) ............................................. - 0.5 V to 7 V Power dissipation .............................................................................................. 2 W Note Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics VCC = 5 V 10 %; VSS = 0 V TA= 0 to 70 C for the SAB 80515/80535 T A = - 40 to 85 C for the SAB 80515/80535-T40/85 T A = - 40 to110 C for the SAB 80515/80535-T40/110 Symbol Limit values min. max. 0.8 VCC - 0.5 VC C + 0.5 - 5.5 0.45 0.45 - - V V V V V V V V V - - XTAL1 to VSS - V CC = 0 V IOL = 1.6 mA1) IOL = 3.2 mA 1) IOH = - 80 A IOH = - 400 A Unit Test condition Parameter Input low voltage Input high voltage ) (except RESET, XTAL2 Input high voltage to XTAL2 Input high voltage to RESET Power down voltage Output low voltage ports 1, 2, 3, 4, 5 Output low voltage port 0, ALE, PSEN Output high voltage ports 1, 2, 3, 4, 5 Output high voltage port 0, ALE, PSEN 1) V IL VIH VIH1 VIH2 VPD VOL VOL1 VOH VOH1 - 0.5 2.0 2.5 3.0 3 - - 2.4 2.4 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and ports 1,3,4,5. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-0 transitions during bus operation. Semiconductor Group 29 SAB 80515/80535 DC Characteristics (cont'd) Parameter Symbol Limit values min. Logic 0 input current ports 1, 2, 3, 4, 5 Logic 0 input current XTAL2 Input low current to RESET for reset Input leakage current to port 0, EA AN0 - AN7 Power supply current:) SAB 80515/80535 SAB 80515/80535-T40/85 SAB 80515/80535-T40/110 Power-down current Capacitance of I/O buffer 1) Unit Test condition max. - 800 - 2.5 - 500 A I IL I IL2 IIL3 ILI - - - - VIL = 0.45 V XTAL1 = VSS VIL = 0.45 V VIL = 0.45 V 0 V < VIN < VCC mA A A 10 ICC ICC ICC IPD CIO - - - - - 210 230 230 3 10 mA mA mA mA pF all outputs disconnected VCC = 0 V fC =1 MHz Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and ports 1,3,4,5. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-0 transitions during bus operation. Semiconductor Group 30 SAB 80515/80535 A/D Converter Characteristics VCC = 5 V 10 %; VSS = 0 V; VAREF = VCC 5 %; VAGND = VSS 0.2 V; TA = 0 to + 70 C for SAB 80515/80535 VIntAREF - VIntAGND 1 V; TA = - 40 to + 85 C for SAB 80515/80535 - T40/85 Parameter Symbol min. Analog input voltage VAINPUT Limit values typ. max. VAREF+ V 0.2 - 2 tCY 5 tCY 13 tCY 1 1 1 1 2 5 30 pF s s s LSB LSB LSB LSB LSB mA mV - 1) Unit Test condition VAGND- - 0.2 - - - - - 25 - - - 1/2 1/2 1/2 1/2 1 - 5 Analog input capacitance CI Load time Sample time (incl. load time) Conversion time (including sample time) Differential non-linearity Integral non-linearity Offset error Gain error Total unadjusted error VAREF supply current Internal reference error 1) tL tS tC DNLE INLE - - - VIntAREF = V AREF = VCC VIntAGND = V AGND = VSS 2) 2) 2) TUE I REF VIntREFER - - The internal resistance of the analog source must be low enough to assure full loading of the sample capacitance (C I )during load time (t L). After charging of the internal capacitance (CI ) in the load time (t L) the analog input must be held constant for the rest of the sample time (tS). The differential impedance rD of the analog reference voltage source must be less than 1 k at reference supply voltage. 2) Semiconductor Group 31 SAB 80515/80535 AC Characteristics V CC = 5 V 10 %; V SS = 0 V; (C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF) T A = 0 to + 70 C; for SAB 80515/80535 T A = - 40 to + 85 C; for SAB 80515/80535 - 40/85 Parameter Symbol 12 MHz clock min Program Memory Characteristics Cycle Time ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN *) Limit values Variable clock 1/t CLCL = 1.2 MHz to 12 MHz min. max. Unit max. t CY t LHLL t AVLL t LLAX1 t LLIV t LLPL t PLPH t PLIV t PXIX t PXIZ *) t PXAV *) t A VIV t A ZPL 1000 127 53 48 - 58 215 - 0 - 75 - 0 - - - - 233 - 12 t C LCL 2 t C LCL - 40 t C LCL - 30 t C LCL - 35 - t C LCL - 25 3 t C LCL - 35 - - - - 4 t C LCL - 100 - - ns ns ns ns ns ns ns ns ns ns ns ns ns 150 - 63 - 302 - - 0 - 3 t C LCL -100 - t C LCL - 20 - t C LCL - 8 - 5 t C LCL - 115 - 0 Interfacing the SAB 805156 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Semiconductor Group 32 SAB 80515/80535 Parameter Symbol 12 MHz clock min max. Limit values Variable clock 1/t CLCL = 1.2 MHz to 12 MHz min. max. Unit External Data Memory Characteristics RD pulse width WR pulse width Address hold after ALE RD to valid data in DATA hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD t RLRH t WLWH t LLAX2 tRLDV t RHDX t RHDZ t LLDV t AVDV t LLWL t AVWL t WHLH t QVWX t QVWH t WHQX t RLAZ 400 400 132 - 0 - - - 200 203 43 33 433 33 - - - - 252 - 97 517 585 300 - 6 tCLCL - 100 6 tCLCL - 100 2 tCLCL - 35 - 0 - - - 3 tCLCL- 4 CLCL - 2 tCLCL - - - 5 tCLCL - ns ns ns 165 ns ns - 70 150 ns ns 8 tCLCL - 9 tnCLCL - 165 ns ns ns ns ns ns ns ns 50 130 3 tCLCL + - 50 123 - - - 0 tCLCL- 40 tCLCL - 50 7 tCLCL - tCLCL + 40 - - - 0 150 tCLCL - 50 - Semiconductor Group 33 SAB 80515/80535 Waveforms Program Memory Read Cycle Semiconductor Group 34 SAB 80515/80535 Data Memory Read Cycle Recommended Oscillator Circuits Semiconductor Group 35 SAB 80515/80535 AC Characteristics (cont'd) Parameter Symbol Limit values Variable clock Frequ. = 1.2 MHz to 12 MHz min. External Clock Drive XTAL2 Oscillator period High time Low time Rise time Fall time Oscillator period tCLCL t CHCX tCLCX tCLCH tCHCL tCLCL 83.3 20 20 - - Unit max. 833.3 tCLCL - tCLCX tCLCL - t CHCX 20 20 833.3 ns ns ns ns ns ns 83.3 External Clock Cycle Semiconductor Group 36 SAB 80515/80535 A.C. testing inputs are driven at 2.4 V for a logic "1" and at 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and at 0.8 V for a logic "0". For timing purposes, the float state is defined as the point at which a P0 pin sinks 3.2 mA or sources 400 A at the voltage test levels. A.C. Testing Input, Output, Float Waveforms Semiconductor Group 37 SAB 80515/80535 AC Characteristics (cont'd) Parameter Symbol 12 MHz clock Limit values Variable clock 1/t CLCL = 1.2 MHz to 12 MHz min. max. Unit min. System Clock Timing ALE to CLKOUT CLKOUT high time CLKOUT low time CLKOUT low to ALE high tLLSH tSHSL tSLSH tSLLH 543 127 793 43 max. - - - 123 7 tCLCL - 40 2 tCLCL - 40 10 tCLCL - 40 tCLCL - 40 - - - tCLCL + 40 ns ns ns ns System Clock Timing Semiconductor Group 38 SAB 80515/80535 ROM Verification Characteristics T A = 25 C 5 C; V CC = 5 V 10 %; V SS = 0 V Parameter Symbol min Limit values max. Unit ROM Verification Address to valid data ENABLE to valid data tAVQV tELQV - - 48 tCLCL1 48 tCLCL1 48 tCLCL1 6 ns ns ns MHz Data float after ENABLE tEHOZ Oscillator frequency 1/tCLCL 0 4 Address: P1.0-P1.7 P2.0-P2.4 Data: Inputs: Port 0 = A0-A7 = A8-A12 = D0-D7 P2.5-P2.6, PSEN = VSS ALE, EA = VIH RESET = VIL ROM Verification Semiconductor Group 39 SAB 80515/80535 Package Outlines Plastic Package, P-LCC-68 - SMD (Plastic Leaded Chip-Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Dimensions in mm Semiconductor Group 40 |
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